학술논문
A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi
Document Type
Conference
Author
Source
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Custom integrated circuits Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000. :319-322 2000
Subject
Language
Abstract
A PRML read/write IC operating up to 450 Mbit/s is presented. The chip implements a 16-state EPR4 parity check time variant Viterbi detector and a digital servo. A 24/26 code with parity check improves the robustness to white noise, media noise and to off-track conditions. The device is integrated in a mature 0.35 /spl mu/m BiCMOS technology with a die size of 13 mm/sup 2/ (step and repeat) and dissipates 1.9 W (in read mode) at 450 Mbit/s.