학술논문
Design of High Gain Operational Transconductance Amplifiers in 180 nm CMOS technology
Document Type
Conference
Source
2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER) Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER). 2019 IEEE International Conference on. :1-4 Aug, 2019
Subject
Language
Abstract
This paper presents two architectures of two-stage Operational Transconductance Amplifiers (OTAs). To achieve high gain, folded cascode topology is used. The first architecture uses an external bias which can be controlled independent of the OTA gain and bandwidth, while the second architecture uses a self-bias which reduces the power dissipation at the expense of restricted control over gain and bandwidth tuning. The two topologies are implemented using UMC 180 nm CMOS 1P9M technology. Both the architectures provide higher gain and consume less power in comparison to the previously published results.