부산대학교 도서관

Single photon counting hybrid pixel detector technology with short gate capability has been chosen to perform time-resolved pump-probe experiments in the energy range 5f-15 keV at SOLEIL Synchrotron. The detector prototypes, based on the UFXC32k [1] readout chip, were developed for this initial purpose due to several very interesting performances of the chip such as high readout speed, high count-rate capabilities, and moderate pixel size. The prototype cameras can reach the framerate of 20 kfps in fastest configuration with current DAQ (2-bits readout, DAQ limited). After completion of small-size prototypes, a new detector demonstrator of medium size with 8 chips is under development. This represents several new challenges in the detector development program at SOLEIL, as the new camera will provide improved performance with multiple acquisition modes. This paper presents a new data acquisition system and image recovering architecture dedicated for this demonstrator. It is based on a Xilinx Virtex-7 FPGA (Field Programmable Gate Arrays) and PandaBlocks firmware for control and status. The DAQ (Data AcQuisition) system enables to stream data from the detector with four 10 Gb/s Ethernet links reaching up to 40 Gb/s bandwidth through four high-speed transceivers. The new architecture allows for reading 8 chips simultaneously, without reducing images frequency.