학술논문
A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography
Document Type
Conference
Author
Nackaerts, A.; Ercken, M.; Demuynck, S.; Lauwers, A.; Baerts, C.; Bender, H.; Boulaert, W.; Collaert, N.; Degroote, B.; Delvaux, C.; de Marneffe, J.F.; Dixit, A.; De Meyer, K.; Hendrickx, E.; Heylen, N.; Jaenen, P.; Laidler, D.; Locorotondo, S.; Maenhoudt, M.; Moelants, M.; Pollentier, I.; Ronse, K.; Rooyackers, R.; Van Aelst, J.; Vandenberghe, G.; Vandervorst, W.; Vandeweyer, T.; Vanhaelemeersch, S.; Van Hove, M.; Van Olmen, J.; Verhaegen, S.; Versluijs, J.; Vrancken, C.; Wiaux, V.; Jurczak, M.; Biesemans, S.
Source
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. Electron devices meeting Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International. :269-272 2004
Subject
Language
Abstract
This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate length, 70nm tall & 35nm wide fins, 35nm wide HDD spacer are used. Low-tilt extension/HALO implants, NiSi and Cu/low-k BEOL are some of the key features. This is an experimental demonstration of a fully working tall triple gate SRAM cell with the smallest cell size ever reported.