학술논문

Architecture and Algorithm Co-Design Framework for Embedded Processors in Event-Based Cameras
Document Type
Conference
Source
2021 IEEE International Symposium on Circuits and Systems (ISCAS). :1-5 May, 2021
Subject
Components, Circuits, Devices and Systems
Visualization
Program processors
Neuromorphics
Heuristic algorithms
Computer architecture
Cameras
Object tracking
event-based vision processing
embedded computing
RISC-V
FPGA SoC
Language
ISSN
2158-1525
Abstract
Neuromorphic cameras that offer low latency and dynamic scene sensing are emerging as a viable technology for energy-aware embedded perceptual systems. In this paper we report on neuromorphic architecture and algorithm exploration for an event-based accelerator for neuromorphic cameras. The system includes a RISC-V CPU and associated peripherals that capture and process event-based visual data coming from a neuromorphic dynamic vision sensor. Mapped into a reconfigurable computing platform (FPGA), we demonstrate a set of event-based visual processing tasks including noise filtering, corner detection, and object tracking.