부산대학교 도서관

Neuromorphic TinyML (vTinyML) aims at solving problems in machine perception and intelligence at the edge that necessitate low latency processing, using low resource processors that have neuromorphic event-based sensory interfaces and neuromorphic accelerators. In this paper, we report on a neuromorphic TinyML architecture (vMCU) which can be leveraged to be deployed to process data from event-based sensors on the edge. The core of the system is a RISC-V CPU from SiFive which is used for algorithm development. The CPU interfaces with a set of communication and computation peripherals which are comprised most notably of an event-based physical interface which has a 256Kib FIFO, a programmable 47-bit time-stamping unit and an embedded Compute in Memory (CiM) associative processor employing charge based processing and a pseudo-DRAM cell primitive. The vMCU SOC was fabricated in 65nm CMOS, has a die size of $7\text{mm}\times 4\text{mm}$, runs at 100MHz and has a maximum event throughput at its physical interface of 17Meps. Binary and integer operations on long bit vectors using the CiM accelerator capabilities take a few fJ per Op. vMCU capability consumes 30mW and is demonstrated in various tasks for embedded applications, including character recognition from a DAVIS240C event-based camera.