학술논문
DFT techniques for memory macro with built-in ECC
Document Type
Conference
Author
Source
2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05) Workshop on memory technology, design and testing Memory Technology, Design, and Testing, 2005. MTDT 2005. 2005 IEEE International Workshop on. :109-114 2005
Subject
Language
ISSN
1087-4852
Abstract
DFT techniques to implement ECC circuitry on memory macro with no additional test cost are proposed. New methodology to design a Hamming code matrix is used to achieve whole ECC system testing with standard memory BIST and conventional test sequence. The proposed ECC techniques are implemented in a 512Kb SRAM macro and demonstrated by hardware characterization with 90nm technology.