학술논문
Several driving configurations with low-voltage input control for a planar power switch
Document Type
Periodical
Author
Source
IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 19(1):147-154 Feb, 1984
Subject
Language
ISSN
0018-9200
1558-173X
1558-173X
Abstract
Several flip-flop control configurations for the coplanar CMOS power switch are proposed that lead to a reduction of the on-chip power dissipation and input control voltage. Moreover, the switch becomes less sensitive to tolerances in the capacitive voltage divider controlling the gate of the output transistor. An acceptable tradeoff between chip area consumed by the flip-flop arrangement, reduction of the on-chip power dissipation, and input control voltage is possible. The on-chip low-voltage control circuitry is also described.