학술논문
Distributed clock generator for synchronous SoC using ADPLL network
Document Type
Conference
Author
Source
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference Custom Integrated Circuits Conference (CICC), 2013 IEEE. :1-4 Sep, 2013
Subject
Language
ISSN
0886-5930
2152-3630
2152-3630
Abstract
This paper presents a novel architecture of on-chip clock generation employing a network of oscillators synchronized by the distributed all-digital PLLs (ADPLLs). The implemented prototype has 16 clocking domains operating synchronously in a frequency range of 1.1-2.4 GHz. The synchronization error between the neighboring clock domains is less than 60 ps. The fully digital architecture of the generation offers flexibility and efficient synchronization control suitable for use in synchronous SoCs.