부산대학교 도서관

This paper demonstrates the scalability of the dual damascene (DD) integration scheme for BEOL interconnects below 28 nm pitch. To accomplished this, we developed and demonstrated two novel process flows. First, we extend Cu-based damascene interconnect with a selectively deposited TaN barrier that reduced via resistance without compromising reliability. Second, we introduced an innovative dual metallization scheme with metallurgy chosen for the enhanced performance of fine and wide lines. These process innovations enable a significant improvement in via, signal and power line resistances. We discuss the corresponding implications towards performance in terms of signal delay, parasitic voltage, and FPG gain (FET performance gauge) analysis. Our simulations based on experimental data show that extending Cu metallization can enable next-generation interconnects (20-24nm pitch) for low power mobile-like design solutions. For high-performance computing (HPC) applications, dual metallurgy with high aspect ratio power rails provides the best performance.