학술논문

Impact of scribe line (kerf) defectivity on wafer yield
Document Type
Conference
Source
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2018 29th Annual. :374-378 Apr, 2018
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Power, Energy and Industry Applications
Metrology
Inspection
Silicon
Image edge detection
Optical imaging
Substrates
Lithography
Language
ISSN
2376-6697
Abstract
Scribe line (also known as kerf or frame) is an area in a silicon wafer which is used to separate individual die at the end of wafer processing. This area also contains features which assist in the manufacturing process but are not present in a final product. Examples of such features include lithography alignment and overlay marks, thickness measurement pads and electric test macros. The overall design of scribe line features can be drastically different from the die layout. In the chemical mechanical polishing (CMP) process, regions of low pattern density have higher polishing rates compared to those of high pattern density, leading to overpolishing or "dishing". The scribe line, with intermittent regions of low and high pattern density, is naturally more prone to dishing, an issue which is exacerbated by thickness variation at the wafer edge. In this work, we present examples of how interaction between process variation and scribe line design can result in yield loss for the prime die.