학술논문
A capacitorless twin-transistor random access memory (TTRAM) on SOI
Document Type
Conference
Author
Source
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005. Custom Integrated Circuits Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005. :435-438 2005
Subject
Language
ISSN
0886-5930
2152-3630
2152-3630
Abstract
We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2Mb test device has been fabricated on 130nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100ms at 80/spl deg/C. TTRAM process is compatible with the conventional SOI-CMOS and never requires any additional processes. A 6.1ns row-access time is achieved and 250MHz operation can be realized by using 2bank 8b-burst mode.