학술논문

SeqL+: Secure Scan-Obfuscation With Theoretical and Empirical Validation
Document Type
Periodical
Source
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 42(5):1406-1410 May, 2023
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Flip-flops
Logic gates
Security
Complexity theory
Resists
Resilience
Iterative algorithms
IP piracy
scan-chains
scan-scrambling
Language
ISSN
0278-0070
1937-4151
Abstract
Scan-obfuscation is a powerful methodology to protect Silicon-based intellectual property from theft. Prior work on scan-obfuscation in the context of logic-locking have unique limitations, which are addressed by our previous work, SeqL, which looks at functional output corruption to obfuscate scan-chains, but is unable to resist removal attacks on circuits with inadequate number of flip-flops without feedback. To address this issue, we propose to scramble flip-flops with feedback to increase key length without introducing further vulnerabilities. This study reveals the first formulation and complexity analysis of Boolean satisfiability (SAT)-based attack on scan-scrambling. We formulate the attack as a conjunctive normal form (CNF) using a worst-case $\mathcal {O}(n^{3})$ reduction in terms of scramble-graph size $n$ . In order to defeat SAT-based attack, we propose an iterative swapping-based scan-cell scrambling algorithm that has $\mathcal {O}(n)$ implementation time-complexity and $\mathcal {O}(2^{\lfloor ({\alpha.n+1}/{3}) \rfloor })$ SAT-decryption time-complexity in terms of a user-configurable cost constraint $\alpha ~(0 < \alpha \le 1)$ .