부산대학교 도서관

This letter describes a NAND flash memory multichip package (NAND MCP) incorporating a developed LSI interface (IF) Chip (Bridge Chip) in which the IF to and from the solid-state drive (SSD) controller has twice the speed as that of the IF to and from the NAND dies even with multiple packages on each printed circuit board (PCB) channel. This NAND MCP allows to reduce the number of NAND IF channels on the PCB while retaining the total bandwidth of the SSD and increasing the capacity. The Bridge Chip employs a 2:1 frequency multiplying function to bridge the speed gap, a fast-lock phase-locked loop (PLL) with an extended pull-in range and 16-cycle lock time to enhance the IF performance with its input-jitter filtering effect, and equalizers to compensate for intersymbol interference and reflected noise in up to a 4-drop configuration. The Bridge Chip implemented in a 12-nm CMOS process is demonstrated at 6.4 Gb/s/pin with 2.85-pJ/b I/O energy efficiency in a read operation. The NAND MCP incorporating the Bridge Chip and eight 1-Tb NAND dies achieves data transmission to and from field-programmable gate array (FPGA) at twice the speed of the NAND IF in a 2-drop configuration.