학술논문
Backside Thinning Process Development for High-Density TSV in a 3-Layer Integration
Document Type
Conference
Author
Source
2024 IEEE 74th Electronic Components and Technology Conference (ECTC) ECTC Electronic Components and Technology Conference (ECTC), 2024 IEEE 74th. :370-377 May, 2024
Subject
Language
ISSN
2377-5726
Abstract
This paper describes recent developments in the field of high density Through Silicon Vias (TSV) with a focus on the backside thinning flow (grinding, CMP, metrology) for TSV depths of 6μm or lower. Stringent process control was implemented from grinding to CMP finishing steps to obtain remarkably low silicon Total Thickness Variations below 1μm.