학술논문
Side Channel Leakage Assessment Strategy On Attack Resistant AES Architectures
Document Type
Conference
Author
Source
2020 24th International Symposium on VLSI Design and Test (VDAT) VLSI Design and Test (VDAT), 2020 24th International Symposium on. :1-6 Jul, 2020
Subject
Language
Abstract
A leakage assessment / evaluation and comparative analysis on various architectures of masked AES-128 cryptographic algorithm to mitigate the side channel attack is presented. In this work, unmasked and masked implementations of S-Box for AES-128 at micro architecture level and also generation of random mask using True random number generator based on Galois ring oscillator of polynomial 16 is implemented and discussed in detail. Side Channel Leakage is evaluated by Correlation Power Analysis (CPA) and Leakage assessment using Welch's t-test. The implementations are realized in SAKURA-G Side channel evaluation Board. This work quantifies the effectiveness of unmasked and masked AES implementations in side channel mitigation and also identifies the point of leakage and approximate number of traces required to identify the leakage on the adopted mitigation technique is also presented.