학술논문
Electrical modelling of LSCRs in deep submicron CMOS technologies for circuit-level simulation of ESD protection structures
Document Type
Conference
Author
Source
2003 Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (IEEE Cat. No.03CH37440) Bipolar/BiCMOS circuits and technology Bipolar/BiCMOS Circuits and Technology Meeting, 2003. Proceedings of the. :97-100 2003
Subject
Language
ISSN
1088-9299
Abstract
This paper presents an electrical model of a parasitic LSCR that represents the inner currents before and after triggering. It relies on the standard LSCR model before triggering, and on a PiN diode model for the post-triggering behaviour. As an illustration, the model has been validated against silicon in both 0.18/spl mu/m and 0.13/spl mu/m technologies.