학술논문
Relations between system level ESD and (vf-)TLP
Document Type
Conference
Author
Source
2006 Electrical Overstress/Electrostatic Discharge Symposium Electrical Overstress/Electrostatic Discharge Symposium, 2006. EOS/ESD '06.. :136-143 Sep, 2006
Subject
Language
ISSN
2164-9340
Abstract
This paper shows that device robustness for system level ESD scales linearly with device width. Relations between system level failure voltages and TLP failure currents are established. Most compound structures follow the same relations. The exceptions have a different failure mechanism, which is shown to correlate with vf-TLP characterisation. The results enable predictive simulations for system level ESD robust designs.