부산대학교 도서관

Approximate computing (AxC) emerged as a design alternative to boost design efficiency by leveraging the inherent error resiliency of many applications. Recent literature shows attackers could exploit some AxC mechanisms to create new attack surfaces. This work proposes integrity checking and exclusive logic-based methods detect attacks by hardware faults on AxC systems. During ASIC-based synthesis, we investigate the security vulnerabilities of the Approximate Parallel Prefix Adder (AxPPA). We compare the expected output of the designer with the output netlists of ASIC-based synthesis. We propose a verification methodology consisting of a golden model (GM) described in a Simulink model and the DUT represented at the netlist level in a standard cell library after logic synthesis. Experimental results show that the AxPPA has an error range of 1.263 × 10 −5 to 0.0098 concerning the designer’s expected output under ASIC-based synthesis attacks.