학술논문

Standard Cell and Supergates Designs: An Electrical Comparison on 4-Input Logic Functions
Document Type
Conference
Source
2022 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and Systems (ISCAS), 2022 IEEE International Symposium on. :1744-1748 May, 2022
Subject
Components, Circuits, Devices and Systems
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Measurement
Design methodology
Logic gates
Electric variables
Logic functions
Delays
Power dissipation
Cell design automation
static CMOS complex gate
technology mapping
transistor network
glitch power
Language
ISSN
2158-1525
Abstract
This paper presents an electrical study on logic functions with up to 4 inputs designed with a standard cell mapping and two automatically generated supergates methodologies. The results indicate that supergate-based designs reduce the average power in 84.4% of the studied cases while reducing area by 12.9%. Despite the supergate design increasing in average the circuit critical delay by 5.8%, it achieves better power-delay-product in 2823 (70.9%) of the 3982 studied logic functions. The reduction of logic levels is the main factor for gains obtained with supergates due to the glitch power reduction.