부산대학교 도서관

Clock and data recovery (CDR) circuits are crucial components in high speed transceivers. In order to ensure synchronization between data and clock in the most economic way, clock information is embedded into the transmitted data stream. The function of the CDR circuit is to determine not only the frequency at which the incoming signal needs to be sampled, but also the optimal choice of the sampling instant within each symbol interval. This paper discusses the CDR architecture, circuit design and verification of a half-rate clock and data recovery circuit utilizing a proposed new linear phase detector for serial interfaces operating at OC-12/STM-4 data rate, which is 622 Mb/s. The phase detector gain, Kpd is 156 /spl mu/A and the VCO gain, Kvco is 150 MHz/V. This circuit exhibits a BER of 10/sup -8/ and with a power dissipation of less than 25 mW. Design is based upon 0.35 /spl mu/m CMOS fabrication technology with 3.3 V operating voltage.