학술논문
Vertical Channel Transistor (VCT) as Access Transistor for Future 4F2 DRAM Architecture
Document Type
Conference
Author
Feng, Daohuan; Jiang, Yi; Qiu, Yunsong; Zheng, Yuhong; Kim, Harry; Kim, Jaewoo; Chu, Jian; Shao, Guangsu; Liao, Yucheng; Yang, Chen; Hu, Minrui; Zhao, Wenli; Xia, Linjiang; Xiao, Jianfeng; Ma, Di; Cheng, Yuan; Kong, Xiangbo; Lin, Chao; Li, Tianming; Li, Yongjie; Meng, Jingheng; Shao, Kai; Wang, Yan; Yang, Xiaoan; Liu, Xiang; Han, Qinghua; Li, Huiming; Tang, Yanzhe; Liu, Mingde; Wu, Eric; Li, Xiaoping; Huang, Renrui; Zhang, Mingtang; Hou, Long; Pan, Xuan; Jin, Xinwen; Zhao, Shuiping; Han, Dh; Park, Ted; Xiao, Deyuan; Zhao, Chao; Yoo, Abraham
Source
2023 IEEE International Memory Workshop (IMW) Memory Workshop (IMW), 2023 IEEE International. :1-4 May, 2023
Subject
Language
ISSN
2573-7503
Abstract
In this work, a novel 4F 2 VCT (vertical channel transistor) targeting for next generation of DRAM is proposed. We approached process feasibility and device performance of $\mathbf{4 F}^{2}$ VCT by TCAD simulation. Detailed processes such as BL (bit line) and WL (word line) loop have also been discussed to achieve lx node VCT DRAM. For the first time, silicon demonstration for $8\mathrm{~Gb}$ full array VCT with density as high as $198\ \mathrm{Mbit}/\mathrm{mm}^{2}$ is successfully realized. Besides, we also demonstrated standard switching behavior of VCT access transistor with reasonable device performance.