학술논문

Analysis of the Role of Interfacial Layer in Ferroelectric FET Failure as a Memory Cell
Document Type
Periodical
Source
IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 45(4):562-565 Apr, 2024
Subject
Engineered Materials, Dielectrics and Plasmas
Components, Circuits, Devices and Systems
Stress
Degradation
FeFETs
Switches
Iron
Silicon
Hafnium oxide
Ferroelectric
stress
degradation
hole trapping
Language
ISSN
0741-3106
1558-0563
Abstract
By observing temporary and permanent changes in threshold voltage ( ${V}_{\text {T}}$ ) due to the application of unipolar/bipolar stress, it was confirmed that the trap-carrier interaction speed is the cause of failure of the ferroelectric transistor as a memory. As the polarization switching occurs, carriers are trapped in the ferroelectric/interfacial layer (FE/IL), and the hole trap is limited compared to the electron trap due to the slow interaction. IL degrades under bipolar stress due to the high electric field during polarization switching, leading to the acceleration of hole trapping, which has a strong impact on the memory window.