학술논문
Decoupling Capacitor Optimization for 2.5D-ICs With Deep Reinforcement Learning Technique
Document Type
Conference
Author
Source
2024 Conference of Science and Technology for Integrated Circuits (CSTIC) Science and Technology for Integrated Circuits (CSTIC), 2024 Conference of. :1-3 Mar, 2024
Subject
Language
Abstract
In this paper, we proposed a deep reinforcement learning-based design method that provides decoupling capacitor (decap) arrangement approaches on 2.5D integrated circuit (2.5D-IC) designs. The proposed method provides a guideline of decap design to reduce the influence of simultaneous switch noise (SSN). We consider the multi-chiplet design, the capacitors placement constraint, and cost of capacitors when optimizing the power delivery network (PDN) impedance. This method achieves 24% less capacitor requirement when compared to the traditional algorithm.