학술논문
A Workfunction Engineered Middle-Silicon-TiN Gate (MSTG) Cell Transistor in 16Gbit DRAM for High Scalability and Long Data Retention
Document Type
Conference
Author
Source
2023 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2023 International. :1-4 Dec, 2023
Subject
Language
ISSN
2156-017X
Abstract
To mitigate the constraint of the increased gate resistance for dual-workfunction-gate (DWG) cell transistors as a standard platform in the DRAM industry, a Middle-silicon- TiN Gate (MSTG), which replaces the n+-polysilicon with an ultra-thin TiN/silicon interlayer/bulk TiN was demonstrated in a fully integrated 1x-nm 16Gb, and provides superior retention time (2 times) without sacrificing the gate resistance compared to those of the single workfunction gate (SWG). (Keywords: dual-workfunction-gate, gate resistance, TiN, silicon interlayer, retention time, GIDL)