부산대학교 도서관

SIMD instruction-based processing is effective in speeding up highly data-parallel processing such as image recognition. However, processing using the SIMD instruction set requires reconstructed the machine code when changing the number of computing units. Therefore, we have developed RISC-V with vector extensions, a scalable vector extension that can change the number of concurrent parallel operations without changing the machine code, referring to the ARM SVE. There is a problem that RISC-V vectorized machine code cannot be generated due to the lack of a compiler that supports vector extensions. The solution to this problem is to use the assembly code generated by the vectorization compiler for ARM SVE to generate assembly code for RISC-V with vector extensions. By assembling it, we generate RISC-V vectorization machine code. As the first step of implementation, we implement an assembly code translator that performs assembly code translation between the basic instruction set from ARM64 to RISC-V. Since the translated RISC-V program could be executed, it was confirmed that the translation proposed in this study was performed properly.