학술논문

Hardness of Braided Quantum Circuit Optimization in the Surface Code
Document Type
Periodical
Source
IEEE Transactions on Quantum Engineering IEEE Trans. Quantum Eng. Quantum Engineering, IEEE Transactions on. 4:1-7 2023
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Qubit
Optimization
Quantum circuit
Fault tolerant systems
Fault tolerance
Computational complexity
NP-complete problem
Braiding circuits
computational complexity
fault-tolerant quantum computation (FTQC)
NP-complete
PlanarRectilinear3SAT
quantum circuit optimization
surface code
Language
ISSN
2689-1808
Abstract
Large-scale quantum information processing requires the use of quantum error-correcting codes to mitigate the effects of noise in quantum devices. Topological error-correcting codes, such as surface codes, are promising candidates, as they can be implemented using only local interactions in a 2-D array of physical qubits. Procedures, such as defect braiding and lattice surgery, can then be used to realize a fault-tolerant universal set of gates on the logical space of such topological codes. However, error correction also introduces a significant overhead in computation time, the number of physical qubits, and the number of physical gates. While optimizing fault-tolerant circuits to minimize this overhead is critical, the computational complexity of such optimization problems remains unknown. This ambiguity leaves room for doubt surrounding the most effective methods for compiling fault-tolerant circuits for a large-scale quantum computer. In this article, we show that the optimization of a special subset of braided quantum circuits is NP-hard by a polynomial-time reduction of the optimization problem into a specific problem called PlanarRectilinear3SAT.