학술논문

A simple and cost effective video encoder with memory-reducing CAVLC
Document Type
Conference
Source
2005 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and systems Circuits and Systems (ISCAS), 2005 IEEE International Symposium on. :432-435 Vol. 1 2005
Subject
Components, Circuits, Devices and Systems
Communication, Networking and Broadcast Technologies
Engineered Materials, Dielectrics and Plasmas
Costs
Video compression
Hardware
Read only memory
Cameras
Logic devices
Memory architecture
Field programmable gate arrays
Prototypes
Frequency
Language
ISSN
0271-4302
2158-1525
Abstract
In this paper, a simple and cost effective video encoder with memory efficient context adaptive variable length coder (CAVLC) is proposed for low cost multimedia applications. According to the proposed memory reduction architecture, three coding level variables (prefix, length, and codeword) can be calculated on-the-fly to eliminate seven (level-VLCN, N=0 to 6) 28/spl times/64 k bit coding table memories. We implemented the design on a Xilinx FPGA prototyping board. Its maximum working frequency is 28 MHz. And the gate count is 9171 (NAND2) in TSMC 0.35 /spl mu/m technology (only the video encoder). The results show that a low-cost encoder is feasible, and the memory size of the proposed architecture is smaller than others.