학술논문

Impact of Back-Gate Bias and Body-Tie on the DSOI SRAMs Under Total Ionizing Dose Irradiation
Document Type
Periodical
Source
IEEE Transactions on Nuclear Science IEEE Trans. Nucl. Sci. Nuclear Science, IEEE Transactions on. 71(4):469-476 Apr, 2024
Subject
Nuclear Engineering
Bioengineering
Random access memory
Radiation effects
Silicon
Transistors
Power demand
Silicon-on-insulator
Tuning
4k-bit SRAM
back-gate bias strategy
double silicon-on-insulator (DSOI)
total ionization dose (TID)
Language
ISSN
0018-9499
1558-1578
Abstract
The total ionizing mymargin dose mymargin (TID) effect is systematically investigated in the double silicon-on-insulator (DSOI) static random access memory (SRAM) circuits, taking into consideration: silicon film thicknesses, floating/unfloating body, and back-gate bias. It is experimentally demonstrated that the SRAM circuits with thinner silicon layer (45 nm) and floating-body transistors exhibit better radiation tolerance, with a corresponding decrease in read current by 3.8% and an increase in access time by 34.7%. This can be attributed to enhanced back-gate tuning ability, which increased from 2.17% to 8.62% for nMOS and from 8.6% to 34.7% for pMOS. A back-gate bias of −3 V is sufficient to compensate for the degradation with total dose accumulated up to 1 Mrad(Si). Technology computer-aided design (TCAD) simulations indicate that the electric field gradually saturates near the first buried oxide (BOX) for a thicker silicon layer, weakening the modulation ability of back-gate bias. Compared with floating devices, the tuning range is reduced for devices with body-tie (unfloating body), and higher back-gate voltages can significantly strengthen the electric field in the channel, around three times. This results in a substantial increase in the channel current, implying that the back-gate bias cannot be increased unrestrictedly.