학술논문

Design of Low Voltage Vertical Channel Face-tunneling TFET Using Ge/SiGe Materials and Its SRAM Circuit Performance
Document Type
Conference
Source
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) VLSI Technology, Systems and Applications (VLSI-TSA), 2020 International Symposium on. :132-133 Aug, 2020
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Power, Energy and Industry Applications
TFETs
Silicon germanium
Tunneling
Random access memory
Logic gates
Capacitance
Topology
Language
Abstract
A novel vertical channel face-tunneling field effect transistor (VC-TFET) using Ge/SiGe material is proposed in this paper. The proposed device structure enhances the on-state drive current without increasing the device footprint and also provides lower off-state leakage current, steeper sub-threshold slope and higher $I_{on}/I_{off}$ current ratio compared to the other TFETs. The design of SiGe-material in the drain region suppresses the leakage current, and the channel region with small bandgap Ge enhances the tunneling current. Additionally, the complementary vertical channel TFET is also used to demonstrate the SRAM circuit performance for low power application. Novel SRAM topologies are proposed to eliminate the read disturb and enhance the RSNM/WSNM of SRAM.