학술논문

Gate-stack engineering for self-aligned Ge-gate/SiO2/SiGe-channel Insta-MOS devices
Document Type
Conference
Source
2015 Silicon Nanoelectronics Workshop (SNW) Silicon Nanoelectronics Workshop (SNW), 2015. :1-2 Jun, 2015
Subject
Components, Circuits, Devices and Systems
Logic gates
Silicon
Silicon germanium
Oxidation
Substrates
Capacitors
Capacitance-voltage characteristics
Language
ISSN
2161-4636
2161-4644
Abstract
We reported a first-of-its-kind, self-aligned gate-stack heterostructure of Ge-nanoshpere-gate/SiO 2 /SiGe-channel on Si in a single-step approach through selective oxidation of a SiGe nano-patterned pillar over a Si 3 N 4 buffer layer on Si substrate. Good tunability on the Ge-nanoshpere size, SiO 2 thickness, and SiGe-shell thickness provides a practically-achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices with size-tunable Ge gates, SiO 2 gate oxide, and SiGe channels. Detailed interfacial morphologies and structural properties between the Ge nanosphere/SiO 2 and SiO 2 /SiGe-channel were examined using transmission electron microscopy, energy dispersive x-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Both Al/SiO 2 /Ge-nanospheres and NiGe/SiO 2 /SiGe MOS capacitors exhibit quite low interface trap densities of 3–5×10 11 cm −2 eV 1 , which is beneficial for advanced Ge MOS applications.