부산대학교 도서관

Recent microprocessors improve performance by extracting various levels of parallelism. Among these, out-of-order processors focus on ILP to improve performance. On the other hand, out-of-order processors consume a lot of power because they fetch and decode many instructions.We propose a Decoded Instruction Cache (DIC), in which the control signals generated by decoding RISC instructions are stored as decoded instructions in the DIC. The scheme improves performance and reduces power consumption because the results of fetch and decode can be reused. The DIC also supports multi-threaded execution, so TLP is also improved.When implemented in a multithreaded RISC processor, the DIC improves IPC by 2.39%.