학술논문
Power efficient AES core for IoT constrained devices implemented in 130nm CMOS
Document Type
Conference
Author
Source
2017 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and Systems (ISCAS), 2017 IEEE International Symposium on. :1-4 May, 2017
Subject
Language
ISSN
2379-447X
Abstract
The Internet of Things (IoT) constrained devices show the urgent need for low power data security hardware cores. This paper presents a power efficient AES Core fabricated in UMC 130 nm CMOS technology by using Faraday standard cells library. The maximum throughput of the proposed AES Core is up to 2.6 Gb/s consuming about 0.2148 mW/MHz at 1.2V. The Dynamic Voltage and Frequency Scaling (DVFS) technique is applied to reduce the power consumption of the AES Core. The experimental measurements show about 3x reduction in power consumption, consuming about 0.0697 mW/MHz by scaling the supply voltage from 1.2 V to 0.7 V.