부산대학교 도서관

Based on a triple comparator and several digital modules, a semidigital buck dc–dc converter is proposed and fabricated in 65-nm CMOS, for SoC power management. The switching frequency is automatically sliding from dozen kHz to sub-MHz for different load conditions. Experimental results show that the presented dc–dc converter has a high efficiency up to 93%, with an active area less than 0.03 mm 2 , and achieves a peak-to-peak ripple voltage smaller than 3.92 mV and a load-step over/under-shoot voltage lower than 10 mV and the switching frequency of 20–578 kHz, with the supply voltage of 1.8–3.3 V and load current of 1–50 mA. The proposed dc–dc converter with the output voltage covering 1.2–1.8 V also accomplishes a linear regulation less than 0.167% and a load regulation lower than 0.208%. This converter has advantages of small area and low complexity due to semidigital structure, high efficiency and low ripple with a sliding-frequency scheme, and pure-MOS design without on-chip passive devices. The proposed triple-comparator structure based on two groups of offset voltages, benefits the digital implementations of buck dc–dc converters.