학술논문

High Performance AlGaInP-Based Micro-LED Displays With Novel Pixel Structures
Document Type
Periodical
Source
IEEE Photonics Technology Letters IEEE Photon. Technol. Lett. Photonics Technology Letters, IEEE. 33(24):1375-1378 Dec, 2021
Subject
Engineered Materials, Dielectrics and Plasmas
Photonics and Electrooptics
Metals
Indium tin oxide
Dry etching
Power generation
Substrates
Leakage currents
Passivation
Light emitting diodes
Micro-LED display
wafer-bonding
patterned contact
dry etching process
passivation
omnidirectional reflector
Language
ISSN
1041-1135
1941-0174
Abstract
The fabrication process and light extraction efficiency of AlGaInP-based flip-chip micro- light-emitting diode ( $\mu $ -LED) array chips are improved by employing a wafer-bonding process, patterned metal contact, and sidewall passivation layers. The epilayers with indium tin oxide (ITO) can be successfully transferred from the GaAs substrate to the sapphire substrate and bound. Three types of patterned n-metal are employed in the $\mu $ -LED as a self-aligning mask and light reflection layer, where the n-GaAs layer can be partially removed by the wet etching process. The dry etching process of MESA has been optimized by applying the BCl 3 gas in the inductively coupled plasma (ICP) system, which can suppress the etching rate of the sidewall and improve the etching depth uniformity. Consequently, the leakage current of the $\mu $ -LED array chip is decreased from 85 to 7 nA under the bias of −5 V. Moreover, three configurations of the metal contact/n-GaAs structures with Omnidirectional reflector (ODR) have been designed to reduce the emission light absorption, passivating the sidewall of MESA, and enhance the output power. Finally, the 0.52-in red $\mu $ -LED array with a chip size of $100\,\,\mu \text{m}\,\,\times 100\,\,\mu \text{m}$ and resolution of 138 pixels/in is realized when bonded with the drive IC. Consequently, the $\mu $ -LED array chips with ODR and patterned contact show the highest external quantum efficiency of 51.1% and relative output power enhancement of 441% compared to the chip with SiO 2 passivation layer and nonpatterned n-metal contact.