학술논문

Impact of SMT-induced edge dislocation positions to NFET performance
Document Type
Conference
Source
2015 73rd Annual Device Research Conference (DRC) Device Research Conference (DRC), 2015 73rd Annual. :184-184 Jun, 2015
Subject
Components, Circuits, Devices and Systems
Photonics and Electrooptics
Stress
Stacking
Resistance
Logic gates
Silicon
Crystals
Atomic measurements
Language
ISSN
1548-3770
Abstract
In summary, this work highlights the impact of SMT-induced edge-dislocation positions in nFET device design. Based on experimental results and atomic transport simulation, dislocations with reduced proximity and depth would increase the amount of SFs and TDs which induce high parasitic resistance and high I boff leakage current together. Trade-off among strained mobility, parasitic resistance and I boff should be made for advanced device design.