학술논문
A 200 MHz 32 b 0.5 W CMOS RISC microprocessor
Document Type
Conference
Author
Source
1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156) Solid-state circuits Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International. :238-239 1998
Subject
Language
ISSN
0193-6530
Abstract
This custom RISC microprocessor delivers approximately 230 Drystone/MIPS at 200 MHz while dissipating 0.5 W from a 1.5 V internal supply. The internal supply can be biased from 1.5 V to 2.0 V, while the external supply is always biased at 3.3 V. A split supply minimizes power consumption for a given application, while maintaining compatibility with a 3.3 V external environment. The die contains 2.5 M transistors and is 8.24/spl times/9.12 mm/sup 2/. It is fabricated in a 0.35 /spl mu/m, 2.0 V, n-well, single-poly, 3-metal-layer CMOS process. It is packaged in a 208 pin thin quad flat pack.