학술논문

Analysis of an sDFT-PLL for Grid-Forming Control Methods
Document Type
Conference
Source
2020 IEEE 9th International Power Electronics and Motion Control Conference (IPEMC2020-ECCE Asia) Power Electronics and Motion Control Conference (IPEMC2020-ECCE Asia), 2020 IEEE 9th International. :323-330 Nov, 2020
Subject
Power, Energy and Industry Applications
Voltage measurement
Power system stability
Distortion
Harmonic analysis
Stability analysis
Robustness
Phase locked loops
Phase-locked-loop (PLL)
grid-forming
eigenvalue analysis
voltage source converter (VSC)
converter control
Language
Abstract
This paper proposes a robust phase-locked-loop (PLL) approach to identify the grid voltage angle and frequency using the sliding discrete Fourier transform (sDFT). Due to the structure of the sDFT-PLL a separation of fundamental and harmonic oscillation as well as an analysis of the positive sequence is performed. Consequently, distortions in the negative sequence or DC offsets as well as harmonics become strongly attenuated and cannot affect the identified measured values. This PLL method is designed for the application in grid-forming control algorithms, in order to achieve a reduced dynamic response to grid state changes. Thus, by applying the PLL, an adjustment of the contribution for the supply of instantaneous active power – synthetic inertia against angle changes – shall be possible. In this paper, the mathematical model of the PLL approach is described and analyses are executed to determine the stability limit depending on the control dynamics. The robustness against grid distortions is confirmed by simulative and experimental investigations.