학술논문
Synthesis for high performance random logic layout
Document Type
Conference
Source
1990 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and Systems (ISCAS), 1990 IEEE International Symposium on. :885-889 vol.2 1990
Subject
Language
Abstract
Techniques are described which are used by Intel's standard cell place and route system to achieve dense, high-performance results. The system uses a two-step approach to achieve high performance: first reduce the average path length by producing a dense result, and then adjust the result to reduce delay on the slowest paths. The performance improvement process involves interaction between the layout tool and some of Intel's performance verification tools.ETX