학술논문
Construction of an optoelectronic bitonic sorter based on CMOS/InGaAs smart pixel technology
Document Type
Conference
Author
Source
Proceedings of Second International Workshop on Massively Parallel Processing Using Optical Interconnections Massively parallel processing using optical interconnections Massively Parallel Processing Using Optical Interconnections, 1995., Proceedings of the Second International Conference on. :180-187 1995
Subject
Language
Abstract
The Scottish Collaborative Initiative in Optoelectronic Sciences (SCIOS) is developing an optoelectronic parallel sorter using CMOS/InGaAs hybrid technology. We describe the design of a system with the potential of sorting 1024 8-bit words in 10 /spl mu/s. The system is based on 32-by-32 arrays of smart pixels produced by solder-assembly of strained InGaAs/GaAs MQW modulator/detectors with CMOS electronics. These devices are linked by an optical perfect shuffle interconnect. The functionality of each processing node, as required by the algorithm, is selected by optical control signals which are circulated along with the optical data. Various physical constraints, including optics limitations, laser power requirements and heat dissipation, have been investigated.