학술논문
A CMOS Current Sensing Interface With Sub-pA DC Uncertainty
Document Type
Periodical
Source
IEEE Transactions on Circuits and Systems II: Express Briefs IEEE Trans. Circuits Syst. II Circuits and Systems II: Express Briefs, IEEE Transactions on. 71(2):508-512 Feb, 2024
Subject
Language
ISSN
1549-7747
1558-3791
1558-3791
Abstract
This brief presents a CMOS current sensing interface with a dedicated analysis on dc uncertainty, especially the relationship among averaging, standard deviation and Allan variance. The dependence of the Allan variance on various noise sources is analyzed. The noise leakage mechanisms due to circuit nonidealities that lead to dc uncertainty are presented. A general design strategy toward a low dc uncertainty is drawn in this brief. An auto-zeroing (AZ) capacitive transimpedance amplifier (CTIA) is reported for near-zero signal loss and near-perfect noise cancelation to achieve a low dc uncertainty. A prototype design implemented on 180nm CMOS process is presented and the measurement result shows a 73fA dc uncertainty.