학술논문

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography
Document Type
Conference
Source
2006 International Electron Devices Meeting Electron Devices Meeting, 2006. IEDM '06. International. :1-4 Dec, 2006
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Photonics and Electrooptics
Capacitive sensors
Lithography
CMOS technology
Wiring
Delay
FETs
Random access memory
Dielectrics
DSL
Stress
Language
ISSN
0163-1918
2156-017X
Abstract
We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37μm 2 , and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific performance elements includes enhanced dual-stress liner (DSL), advanced eSiGe, stress memorization (SMT), and advanced anneal (AA). The resulting PFET/NFET Idsat values, at Vdd of 1.0V and 45nm GR gate pitch, are 840μA/μm and 1240μA/μm respectively. The global wiring delay achieved with k=2.4 reflects a 20% reduction compared to k=3.0.