부산대학교 도서관

The evolution of silicon dynamic RAM toward higher levels of integration has occurred primarily as a result of decreasing the area in which a single bit is stored. This has been accomplished by reducing the thickness of the storage capacitor insulator, introducing higher dielectric constant materials, and increasing the silicon doping levels. Existing published data are used to explore the consequences and requirements of continuing existing density trends into the 1–4 Mbit range. The results indicate that the stored charge density requirement for planar capacitors will be limited by the resultant electric field both in the insulator and silicon. These limitations are imposed by insulator conduction, tunneling, and silicon impact ionization. It is thus evident that for the projected stored charge density of 30 fC/μm 2 for a 4 Mbit DRAM, new concepts of cell design or operation must be introduced. These may take the form of intermediate voltage level plate circuitry or three-dimensional capacitors such as trench or stacked capacitors.