학술논문
FPGA based control and data acquisition interfaces for PANDA components
Document Type
Conference
Author
Source
2014 19th IEEE-NPSS Real Time Conference Real Time Conference (RT), 2014 19th IEEE-NPSS. :1-3 May, 2014
Subject
Language
Abstract
For the upcoming PANDA detector at FAIR (Darmstadt, Germany), various components for timing distribution, control and data acquisition are being constructed. Design objective is to support testing of detector components in a laboratory environment, while keeping it scalable and use hardware platforms and interfaces already agreed on for the final implementation.