학술논문
Demonstration of low cost TSV fabrication in thick silicon wafers
Document Type
Conference
Author
Source
2014 IEEE 64th Electronic Components and Technology Conference (ECTC) Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th. :1641-1647 May, 2014
Subject
Language
ISSN
0569-5503
2377-5726
2377-5726
Abstract
Low cost wafer-level chip-scale vacuum packaging (WLCSVP) imposes unique constraints on potential implementation of through-silicon vias (TSVs). A WLCSVP requires a relatively thick substrate to prevent mechanical failure. Two approaches for integrating TSVs in thick silicon wafers have been successfully demonstrated. Both approaches enable TSV formation from the backside of a device wafer and are compatible with the requirements of subsequent packaging operations. We achieved low contact resistance between TSVs and frontside Ti/Cu and Al metallization, while demonstrating high isolation resistance and high TSV yield.