학술논문

Degradation Due to Photo-Induced Electron in Top-Gate In-Ga-Zn-O Thin Film Transistors With n− Region Under Negative Bias Stress and Light Irradiation
Document Type
Periodical
Source
IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 44(5):765-768 May, 2023
Subject
Engineered Materials, Dielectrics and Plasmas
Components, Circuits, Devices and Systems
Thermal variables control
Negative bias temperature instability
Logic gates
Stress
Electron traps
Degradation
Thin film transistors
InGaZnO
top-gate structure
thin film transistors (TFTs)
reliability
bias stress
NBTIS
Language
ISSN
0741-3106
1558-0563
Abstract
We investigated the positive threshold voltage ( ${V}_{\text {th}}{)}$ shift with hump and on-current ( ${I}_{\text {on}}{)}$ reduction in top-gate In-Ga-Zn-O (IGZO) thin film transistors (TFTs) after negative gate bias of −20 V at 60°C and light irradiation stress (NBTIS). This degradation can be classified into three types of mechanism. 1. The hump at low gate voltage ( ${V}_{\text {g}}{)}$ is a sub-transistor effect caused by hole trapping at the IGZO/top gate insulator (TGI) interface. 2. The positive shift of ${V}_{\text {th}}$ is caused by the trapped photo-induced electrons at the IGZO/bottom gate insulator (BGI) interface. 3. The ${I}_{\text {on}}$ reduction occurred due to trapped photo-induced electrons at interface between $\text{n}^{-}$ region of IGZO/BGI interface. The electric field induced by trapped electron promotes depletion of the channel region at the IGZO/BGI and IGZO/TGI interface and $\text{n}^{-}$ region of IGZO/BGI interface, which corresponds to a drop in effective gate and drain voltage, respectively. Thus, the positive ${V}_{\text {th}}$ shift and ${I}_{\text {on}}$ reduction occurred due to trapping of photo-induced electron under NBTIS. Based on our proposed mechanism, this degradation was suppressed by the dual-gate structure.