학술논문
Trimming of hard-masks by gaseous Chemical Oxide Removal (COR) for sub-10 nm gates/fins, for gate length control and for embedded logic
Document Type
Conference
Author
Natzle, W.C.; Horak, D.; Deshpande, S.; Chien-Fan Yu; Liu, J.C.; Mann, R.W.; Doris, B.; Hanafi, H.; Brown, J.; Sekiguchi, A.; Tomoyasu, M.; Yamashita, A.; Prager, D.; Funk, M.; Cottrell, P.; Higuchi, F.; Takahashi, H.; Sendelbach, M.; Solecky, E.; Wendy Yan; Tsou, L.; Qingyun Yang; Norum, J.P.; Iyer, S.S.
Source
2004 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (IEEE Cat. No.04CH37530) Advanced semiconductor manufacturing Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop. :61-65 2004
Subject
Language
Abstract
A method for formation and control of silicon gates or fins uses trim of a hard mask by a new gaseous oxide etch. The method decouples final feature size from lithography and from the RIE resist trim/oxide mask open processes. Logic blocks with two separately controlled gate lengths and dielectric thicknesses are embedded on chip. COR control has achieved final size sprads of 1 to 2 nm using measurements from either the factory CDSEM or from a scatterometer integrated on the process tool.