학술논문
A high performance 90nm SOI technology with 0.992 /spl mu/m2 6T-SRAM cell
Document Type
Conference
Author
Khare, M.; Ku, S.H.; Donaton, R.A.; Greco, S.; Brodsky, C.; Chen, X.; Chou, A.; DellaGuardia, R.; Deshpande, S.; Doris, B.; Fung, S.K.H.; Gabor, A.; Gribelyuk, M.; Holmes, S.; Jamin, F.F.; Lai, W.L.; Lee, W.H.; Li, Y.; McFarland, P.; Mo, R.; Mittl, S.; Narasimha, S.; Nielsen, D.; Purtell, R.; Rausch, W.; Sankaran, S.; Snare, J.; Tsou, L.; Vayshenker, A.; Wagner, T.; Wehella-Gamage, D.; Wu, E.; Wu, S.; Yan, W.; Barth, E.; Ferguson, R.; Gilbert, P.; Schepis, D.; Sekiguchi, A.; Goldblatt, R.; Welser, J.; Muller, K.P.; Agnello, P.
Source
Digest. International Electron Devices Meeting, Electron devices meeting Electron Devices Meeting, 2002. IEDM '02. International. :407-410 2002
Subject
Language
Abstract
This paper presents a high performance 90 nm generation SOI CMOS logic technology. Leveraging unique SOI technology features, aggressive ground rules and a tungsten local interconnect rendered the smallest 6T SRAM cell reported to date with a cell area of 0.992 /spl mu/m/sup 2/. In the front-end of line (FEOL), the implementation of super-halo design concepts on SOI substrates with a silicon thickness of 45 nm and an ultra-thin heavily nitrided gate dielectric resulted in highest performance devices. The backend of the line (BEOL) for this technology consists of damascene local interconnect followed by up to 10 levels of hierarchical Cu metallization. It utilizes SiLK/spl trade/ low-K dielectric material with a multilayer hard mask stack.