학술논문
Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor
Document Type
Conference
Author
Source
2018 IEEE International Solid-State Circuits Conference - (ISSCC) Solid-State Circuits Conference - (ISSCC), 2018 IEEE International. :300-302 Feb, 2018
Subject
Language
ISSN
2376-8606
Abstract
Enterprise server processor designs, which operate at extreme high frequencies and power envelopes, depend critically on power supply noise mitigation techniques. With supply voltage scaling, very high current draws, and broad usage of clock gating, advanced solutions are needed for next-generation products to minimize droop mitigation response time, which can be defined as the latency from when a dangerous droop begins until a countermeasure is effective.