부산대학교 도서관

For years the substrate industry has been using SOP (solder on pad) to increase the reliability of flip chip packaging, because SOP is formed by the reflow of solder paste printed on the Cu pad of substrate, and this ensure the largest contact area of Cu pad and SOP. When a flip chip with solder balls is attached on top of a substrate and then they go through reflow process, the solder ball and SOP will melt down and joint together as one piece. On the other hand, SOP will add up overall cost of flip chip packaging in 3 aspects. First of all, the cost to make the SOP which includes the tooling as well as material cost. Secondly, it increases the cycle time for substrate vendor to manufacture the substrate. Normally SOP will require 3 days to complete the process. And finally, there is yield loss of SOP ranging from 5% to 10% depending on package size as well as substrate layer count. Substrate accounts for significant share rate of the cost of flip chip packaging and when it comes to cost down of flip chip packaging, substrate cost is always the first item to be reviewed. Most of the solutions to decrease substrate cost are to replace current materials with cheaper one, rarely the solutions to change existing manufacturing process of substrate. An innovative solution to decrease the cost of substrate is the removing of substrate SOP. This will decrease substrate cost, shorten manufacturing cycle time as well as preventing the yield loss of SOP. On the other hand, the way to join flip chip and substrate will have no SOP and it becomes BOP (bump on pad) design. Broadcom and SPIL has developed BOP tech together by using Broadcom 28nm devices with bump pitch 130um as test vehicle. In this paper, the way to design BOP substrate is provided, and then we build some flip chip packages to verify the feasibility of BOP substrate. Die attach process as well as reflow process has to be optimized for BOP substrate so that Cu pad on substrate can still be fully covered by solder to get good reliability result.